Course Timeline
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This note is written by someone(Gavin Gong, zgong6@ncsu.edu) attending this class, not by the instructor(Dr.Greg Byrd, gbyrd@ncsu.edu) of the course(CSC506). There might be errors.
- Amdahl's Law and Gustafson's Law (calculating speed up caused by adding new processors), read Lecture - Amdahl's Law
- Shared memory and message passing, communication/synchronization method used in multiprocessors, read Lecture - Parallel Programming Models
- Data dependency, loop-carried dependency (includes LDG and ITG), read Lecture - Data Dependency
- Loop parallelism(includes DO-ALL, DO-PIPE, DO-ACROSS, Loop-Distribution), see Lecture - Loop Level Parallelism
- Scheduling in OpenMP, and corresponding clauses, see Lecture - OpenMP Clauses
- Cache organization (including direct-mapped, fully associative, set-associative), performance, cache placement and replacement (LRU and FIFO) policies, cache write policies (including write through, write back), cache inclusion Policy, see Lecture - Memory Hierarchy
- Physical and logical cache organization (private and shared and hybrid cache) for multicore architecture, see Lecture - Cache Design in Multicore Architecture
- Cache coherence problem, cache coherence protocols (bus based cache coherence, coherence on none-bus system, broadcast protocol with p2p Interconnect), see Lecture - Cache Coherence
- Coherence protocols in bus based multi-processor system (invalidate based and update based coherence protocol, write through coherence protocol, MSI, MOE, MOESI), see Lecture - Cache Coherence in Bus-based Multiprocessors
Homework 1 Happens here, see Homework - 1
Midterm exam happens here, see Midterm Exam Note
- The consistency problem, consistency model, atomic instructions, lock implementations (test and set locks, and variants), atomic instruction implementations (load linked, load locked, illustration of atomicity, store conditional), barrier implementations see Lecture - Consistency and Synchronization Problems
- Memory consistency model, strongest consistency model(sequential consistency), weak consistency model, relaxed consistency model, see Lecture - Memory Consistency Models
- Directory Coherence Protocol, it's pros and cons, see Lecture - Directory Coherence Protocol
- Interconnection network architecture, topology, message granularity(Packet Switching and Circuit Switching), routing policy and latency, see Lecture - Interconnection Network Architecture
- Transactional Memory, new illusion on atomicity(compared to locks), conflict detection, Hardware Transactional Memory and speculative locks see Lecture - Transactional Memory
- SIMD programming model (kernel level programming) and execution model(warp execution), see Get Started With CUDA Programming Model and Get Started With CUDA Execution Model
Homework 2 Happens here, see Homework - 2
Final exam happens here, see Final Exam Note